Catalog
3.3-V x4 clock multiplier with 8 outputs
Key Features
• Phase-Locked Loop-Based Multiplier by FourInput Frequency Range: 2.5 MHz to 45 MHzOutput Frequency Range: 10 MHz to 180 MHzLVCMOS/LVTT I/O CompatibleLow Jitter (Cycle-Cycle): ±120 ps Over the Range 75 MHz to 180 MHzDistributes One Clock Input to Two Banks of Four OutputsAuto Frequency Detection to Disable Device (Power-Down Mode)Operates From Single 3.3-V SupplyIndustrial Temperature Range –40°C to 85°C25-On-Chip Series Damping ResistorsNo External RC Network RequiredSpread Spectrum Clock Compatible (SSC)Available in 16-Pin TSSOP PackagePhase-Locked Loop-Based Multiplier by FourInput Frequency Range: 2.5 MHz to 45 MHzOutput Frequency Range: 10 MHz to 180 MHzLVCMOS/LVTT I/O CompatibleLow Jitter (Cycle-Cycle): ±120 ps Over the Range 75 MHz to 180 MHzDistributes One Clock Input to Two Banks of Four OutputsAuto Frequency Detection to Disable Device (Power-Down Mode)Operates From Single 3.3-V SupplyIndustrial Temperature Range –40°C to 85°C25-On-Chip Series Damping ResistorsNo External RC Network RequiredSpread Spectrum Clock Compatible (SSC)Available in 16-Pin TSSOP Package
Description
AI
The CDCVF25084 is a high-performance, low-skew, low-jitter, phase-lock loop clock multiplier. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal including a multiplication factor of four. The CDCVF25084 operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN x four. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a low state. Unlike many products containing PLLs, the CDCVF25084 does not require an external RC network. The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25084 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25084 is characterized for operation from –40°C to 85°C.
The CDCVF25084 is a high-performance, low-skew, low-jitter, phase-lock loop clock multiplier. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal including a multiplication factor of four. The CDCVF25084 operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN x four. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a low state. Unlike many products containing PLLs, the CDCVF25084 does not require an external RC network. The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25084 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25084 is characterized for operation from –40°C to 85°C.