SN74LV8151 Series

10-ch, 2-V to 5.5-V buffers with TTL-compatible CMOS inputs

Catalog

10-ch, 2-V to 5.5-V buffers with TTL-compatible CMOS inputs

Part	Output Type	Number of Circuits	Package / Case	Package / Case	Number of Inputs	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Logic Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Package / Case	Package / Case	Package / Case [custom]	Package / Case [custom]
Texas Instruments SN74LV8151PWRE4	Single-Ended	1	24-TSSOP	0.173 in 4.4 mm	10	12 mA	12 mA	Buffer/Inverter	5.5 V	2 V	24-TSSOP	85 °C	-40 °C	Surface Mount
Texas Instruments SN74LV8151NTG4	Single-Ended	1	24-DIP		10	12 mA	12 mA	Buffer/Inverter	5.5 V	2 V	24-PDIP	85 °C	-40 °C	Through Hole	0.3 in	7.62 mm
Texas Instruments SN74LV8151PWR	Single-Ended	1	24-TSSOP	0.173 in 4.4 mm	10	12 mA	12 mA	Buffer/Inverter	5.5 V	2 V	24-TSSOP	85 °C	-40 °C	Surface Mount
Texas Instruments SN74LV8151PW	Single-Ended	1	24-TSSOP	0.173 in 4.4 mm	10	12 mA	12 mA	Buffer/Inverter	5.5 V	2 V	24-TSSOP	85 °C	-40 °C	Surface Mount
Texas Instruments SN74LV8151DW	Single-Ended	1	24-SOIC		10	12 mA	12 mA	Buffer/Inverter	5.5 V	2 V	24-SOIC	85 °C	-40 °C	Surface Mount			7.5 mm	0.295 in

Catalog

10-ch, 2-V to 5.5-V buffers with TTL-compatible CMOS inputs

Key Features

• 2-V to 5.5-V VCCOperationMax tpdof 15 ns at 5 VSchmitt-Trigger Inputs Allow for Slow Input Rise/Fall TimePolarity Control for Y Outputs Selects True or Complementary LogicTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>>2.3 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationSupports Mixed-Mode Voltage Operation on All PortsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)2-V to 5.5-V VCCOperationMax tpdof 15 ns at 5 VSchmitt-Trigger Inputs Allow for Slow Input Rise/Fall TimePolarity Control for Y Outputs Selects True or Complementary LogicTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>>2.3 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationSupports Mixed-Mode Voltage Operation on All PortsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V VCCoperation. The logic control (T/C\) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When T/C\ is high, the Y outputs are noninverted (true logic ), and when T/C\ is low, the Y outputs are inverted (complementary logic). When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple Schmitt-trigger inverter. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V VCCoperation. The logic control (T/C\) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When T/C\ is high, the Y outputs are noninverted (true logic ), and when T/C\ is low, the Y outputs are inverted (complementary logic). When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple Schmitt-trigger inverter. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.