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CDIP (J)
Integrated Circuits (ICs)

JBP18S030MJ

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Texas Instruments

IC PROM 256MBIT PAR 16CDIP

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CDIP (J)
Integrated Circuits (ICs)

JBP18S030MJ

Active
Texas Instruments

IC PROM 256MBIT PAR 16CDIP

Technical Specifications

Parameters and characteristics for this part

SpecificationJBP18S030MJ
Access Time50 ns
Memory FormatPROM
Memory InterfaceParallel
Memory Organization [custom]8
Memory Organization [custom]32
Memory Size256 bit
Memory TypeNon-Volatile
Mounting TypeThrough Hole
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case7.62 mm, 0.3 in
Package / Case16-CDIP
Supplier Device Package16-CDIP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsTUBE 1$ 110.41
100$ 107.09
250$ 89.16
1000$ 83.01

Description

General part information

JBP18S030 Series

These monolithic TTL programmable read-only memories (PROMs) feature titanium-tungsten (Ti-W) fuse links with each link designed to program in 20 microseconds. The Schottky-clamped versions of these PROMs offer considerable flexibility for upgrading existing designs or improving new designs as they feature full Schottky clamping for improved performance, low-current MOS-compatible p-n-p inputs, choice of bus-drive three-state or open-collector outputs, and improved chip-select access times.

Data can be electronically programmed, as desired, at any bit location in accordance with the programming procedure specified. All PROMs are supplied with a low-logic level output condition stored at each bit location. The programming procedure open-circuits Ti-W metal links, which reverses the stored logic level at selected locations. The procedure is irreversible; once altered, the output for that bit location is permanently programmed. Outputs that have never been altered may late be programmed to supply the opposite output level. Operation of the unit within the recommended operating conditions will not alter the memory content.

A low level at the chip-select input(s) enables each PROM. The opposite level at any chip-select input causes the outputs to be off.