
MC100LVEL33DG
ActiveECL DIVIDE-BY-2 DIVIDER, 2.6 GHZ, 3.3 V, SOIC-8
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MC100LVEL33DG
ActiveECL DIVIDE-BY-2 DIVIDER, 2.6 GHZ, 3.3 V, SOIC-8
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC100LVEL33DG |
|---|---|
| Count Rate | 4 GHz |
| Logic Type | Divide-by-4 |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 2 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 8-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Reset | Asynchronous |
| Supplier Device Package | 8-SOIC |
| Trigger Type | Negative, Positive |
| Voltage - Supply [Max] | 3.8 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
MC100LVEL33 Series
The MC100LVEL33 is an integrated div by 4 divider. The LVEL is functionally equivalent to the EL33 and works from a 3.3 V supply.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple LVEL33's in a system.The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBBshould be left open.
Documents
Technical documentation and resources