The DSP56374 is designed to support a multitude of digital signal processing applications requiring a lot of horsepower in a small package. While the DSP56374 is designed with flexibility and thus is versatile in the types of applications it can support, it does include a powerful set of audio features, including various built-in audio peripherals and embedded software designed to meet the needs of both consumer and automotive audio applications. The DSP56374 provides a wealth of audio processing functions including an operating system, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, and many more. The DSP56374 also supports various matrix decoders and sound field processing algorithms. The DSP56374 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale SymphonyTM DSP family. This design provides a two-fold performance increase over Freescale’s popular DSP56000 core family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, patch module, and direct memory access (DMA). The DSP56374 is available in either a 52-pin or 80-pin TQFP at 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.25 V.Dolby DigitalProLogic IIDolby Headphone (DH)Dolby Virtual Speaker (DVS)1.25 V core with a 3.3 V peripheral I/O.150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25V (0 deg C to 70 deg C for consumer-grade devices; -40 deg C to 85 deg C for automotive devices)Object Code Compatible with the DSP56000 core with highly parallel instruction setData ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic supportProgram Control with position independent code support and instruction cache supportSix-channel DMA controllerLow jitter, PLL based clocking with a wide range of frequency multiplications (1 to 1024), predivider factors (1 to 32) and power saving clock divider (2i: i=0 to 7). Reduces clock noiseInternal address tracing support and OnCE for Hardware/Software debuggingJTAG port