The PCA9518 is an expandable five-channel bidirectional buffer for I2C and SMBus applications. The I2C protocol requires a maximum bus capacitance of 400 pF, which is derived from the number of devices on the I2C bus and the bus length. The PCA9518 overcomes this restriction by separating and buffering the I2C data (SDA) and clock (SCL) lines into multiple groups of 400-pF segments. Any segment-to-segment transition sees only one repeater delay. Each PCA9518 can communicate with other PCA9518 hubs through a 4-wire inter-hub expansion bus. Using multiple PCA9518 parts, any width hub (in multiples of five) can be implemented using the expansion pins, with only one repeater delay and no functional degradation of the system performance.

The PCA9518 does not support clock stretching across the repeater.

The device is designed for 3-V to 3.6-V VCCoperation, but it has 5-V tolerant I2C and enable (EN) input pins. This feature allows for translation from 3 V to 5 V between a master and slave. The enable pin also can be used to electrically isolate a repeater segment from the I2C bus. This is useful in cases where one segment needs to run at 100 kHz while the rest of the system is at 400 kHz. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz, because of the delays added by the repeater.Read more