Specification	MC56F8247MLH

A/D Channels	16 count
A/D Resolution (bits)	12 bit
Connectivity	CANbus, I2C, SPI, LINbus, SCI
Core Processor	56800E
Core Size (Bit Width)	16 Bit
D/A Channels	1 count
D/A Resolution (bits)	12 bit
Mounting Type	Surface Mount
Number of I/O	54
Operating Temperature (Max)	125 °C
Operating Temperature (Min)	-40 °C
Oscillator Type	Internal
Package / Case	64-LQFP
Package Length	10 mm
Package Name	64-LQFP
Package Width	10 mm
Peripherals	WDT, PWM, POR, LVD
Program Memory Depth	24 K
Program Memory Size	48 KB
Program Memory Type	FLASH
Program Memory Width	16
RAM Size Depth	4 K
RAM Size Width	16 bit
Speed	60 MHz
Voltage - Supply (Vcc/Vdd) Maximum	3.6 V
Voltage - Supply (Vcc/Vdd) Minimum	3 V

56F824xx Series

Part	Core Processor	Package / Case	Oscillator Type	Speed	Core Size (Bit Width)	Program Memory Width	Program Memory Depth	Program Memory Size	Number of I/O	Operating Temperature (Max)	Operating Temperature (Min)	A/D Channels	A/D Resolution (bits)	D/A Channels	D/A Resolution (bits)	Voltage - Supply (Vcc/Vdd) Maximum	Voltage - Supply (Vcc/Vdd) Minimum	Program Memory Type	Package Length	Package Name	Package Width	RAM Size Width	RAM Size Depth	Mounting Type	Peripherals	Connectivity
NXP USA Inc. MC56F8247MLH	56800E	64-LQFP	Internal	60 MHz	16 Bit	16	24 K	48 KB	54	125 °C	-40 °C	16 count	12 bit	1 count	12 bit	3.6 V	3 V	FLASH	10 mm	64-LQFP	10 mm	16 bit	4 K	Surface Mount	LVD POR PWM WDT	CANbus I2C LINbus SCI SPI

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$	Updated

Digikey	N/A	0	$ 8.07	1m+
		11860	$ 8.07
Mouser	N/A	1	$ 15.11	1m+
		10	$ 11.48
		25	$ 11.01
		50	$ 11.00
		100	$ 9.70
		250	$ 9.22
		500	$ 8.08
		800	$ 7.89
Newark	Each	500	$ 8.01	1m+

CAD

3D models and CAD resources for this part

Description

General part information

56F824xx Series

CoreEfficient 56800E digital signal processor (DSP) engine with modified Harvard architectureAs many as 60 million instructions per second (MIPS) at 60 MHz core frequency155 basic instructions in conjunction with up to 20 address modes32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical operationSingle-cycle 16 X 16-bit parallel multiplier-accumulator (MAC)

Efficient 56800E digital signal processor (DSP) engine with modified Harvard architecture

As many as 60 million instructions per second (MIPS) at 60 MHz core frequency

Documents

Technical documentation and resources

MC56F8247MLH | Datasheet

Datasheet

Product Change Notice EN

Datasheet