Integrated Circuits (ICs)

ADS62P29IRGCT

Active

DUAL-CHANNEL, 12-BIT, 250-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsDesign Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)+9

Integrated Circuits (ICs)

ADS62P29IRGCT

Active

Texas Instruments

DUAL-CHANNEL, 12-BIT, 250-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)

Deep-Dive with AI

DocumentsDesign Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)+9

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	ADS62P29IRGCT

Architecture	Pipelined
Configuration	S/H-ADC
Data Interface	LVDS - Parallel, Parallel
Features	Simultaneous Sampling
Input Type	Differential
Mounting Type	Surface Mount
Number of A/D Converters	2
Number of Bits	12 bits
Number of Inputs	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Package / Case	64-VFQFN Exposed Pad
Ratio - S/H:ADC	1:1
Reference Type	External, Internal
Sampling Rate (Per Second)	250 M
Supplier Device Package	64-VQFN (9x9)
Voltage - Supply, Analog [Max]	3.6 V
Voltage - Supply, Analog [Min]	3.15 V
Voltage - Supply, Digital [Max]	1.9 V
Voltage - Supply, Digital [Min]	1.7 V

ADS62P29 Series

Dual-Channel, 12-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

Part	Sampling Rate (Per Second)	Package / Case	Data Interface	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Input Type	Number of Inputs	Reference Type	Supplier Device Package	Features	Configuration	Number of A/D Converters	Number of Bits	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Architecture	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Ratio - S/H:ADC	Utilized IC / Part	Supplied Contents
Texas Instruments ADS62P29IRGCT	250 M	64-VFQFN Exposed Pad	LVDS - Parallel Parallel	1.7 V	1.9 V	Differential	2	External Internal	64-VQFN (9x9)	Simultaneous Sampling	S/H-ADC	2	12 bits	3.15 V	3.6 V	Pipelined	Surface Mount	85 °C	-40 °C	1:1
Texas Instruments ADS62P29EVM	250 M		Parallel Serial									2	12 bits								ADS62P29	Board(s)
Texas Instruments ADS62P29IRGCR	250 M	64-VFQFN Exposed Pad	LVDS - Parallel Parallel	1.7 V	1.9 V	Differential	2	External Internal	64-VQFN (9x9)	Simultaneous Sampling	S/H-ADC	2	12 bits	3.15 V	3.6 V	Pipelined	Surface Mount	85 °C	-40 °C	1:1
Texas Instruments ADS62P29IRGC25	250 M	64-VFQFN Exposed Pad	LVDS - Parallel Parallel	1.7 V	1.9 V	Differential	2	External Internal	64-VQFN (9x9)	Simultaneous Sampling	S/H-ADC	2	12 bits	3.15 V	3.6 V	Pipelined	Surface Mount	85 °C	-40 °C	1:1

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 151.67
	Digi-Reel®	1	$ 163.74
	Tape & Reel (TR)	250	$ 136.72
Texas Instruments	SMALL T&R	1	$ 140.73
		100	$ 127.38
		250	$ 123.74
		1000	$ 121.32

Description

General part information

ADS62P29 Series

The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

Documents

Technical documentation and resources

Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)

Application note

Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)

Application note

Dual Channel 14-/12-Bit, 250/210 MSPS ADC with DDR LVDS & Parallel CMOS Outputs datasheet (Rev. B)

Data sheet

ADS62P29IRGCT

Deep-Dive with AI

ADS62P29IRGCT

Deep-Dive with AI

Technical Specifications

ADS62P29 Series

Pricing

Description

ADS62P29 Series

Documents

Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)

Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)

CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters

QFN Layout Guidelines

Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio

Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)

TSW4200 Demonstration Kit User's Guide (Rev. C)

Phase Noise Performance and Jitter Cleaning Ability of CDCE72010

Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)

CDCE62005 as Clock Solution for High-Speed ADCs

Dual Channel 14-/12-Bit, 250/210 MSPS ADC with DDR LVDS & Parallel CMOS Outputs datasheet (Rev. B)

ADS62P29 Series