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16-DIP SOT38-1
Integrated Circuits (ICs)

CD74ACT161E

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Texas Instruments

SYNCHRONOUS PRESETTABLE BINARY COUNTERS WITH ASYNCHRONOUS RESET

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16-DIP SOT38-1
Integrated Circuits (ICs)

CD74ACT161E

Active
Texas Instruments

SYNCHRONOUS PRESETTABLE BINARY COUNTERS WITH ASYNCHRONOUS RESET

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74ACT161E
Count Rate80 MHz
DirectionUp
Logic TypeBinary Counter
Mounting TypeThrough Hole
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
ResetAsynchronous
Supplier Device Package16-PDIP
TimingSynchronous
Trigger TypePositive Edge
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.74
10$ 0.66
25$ 0.63
100$ 0.52
250$ 0.48
500$ 0.43
656$ 0.46
1000$ 0.40
Texas InstrumentsTUBE 1$ 0.88
100$ 0.68
250$ 0.50
1000$ 0.36

Description

General part information

CD74ACT161 Series

The ’ACT161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.

These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function is asynchronous. A low level at the clear (CLR)\ input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD)\, or enable inputs.

Documents

Technical documentation and resources