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SN74LVTH162373DGGR

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Texas Instruments

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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TSSOP (DGG)
Integrated Circuits (ICs)

SN74LVTH162373DGGR

Active
Texas Instruments

3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVTH162373DGGR
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low [custom]12 mA
Current - Output High, Low [custom]12 mA
Independent Circuits2
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case48-TFSOP
Package / Case0.24 in
Package / Case [custom]6.1 mm
Supplier Device Package48-TSSOP
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]2.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.60
10$ 1.43
25$ 1.35
100$ 1.11
250$ 1.04
500$ 0.92
1000$ 0.73
Digi-Reel® 1$ 1.60
10$ 1.43
25$ 1.35
100$ 1.11
250$ 1.04
500$ 0.92
1000$ 0.73
Tape & Reel (TR) 2000$ 0.68
6000$ 0.64
10000$ 0.62
Texas InstrumentsLARGE T&R 1$ 1.18
100$ 0.91
250$ 0.67
1000$ 0.48

Description

General part information

SN74LVTH162373 Series

The 'LVTH162373 devices are16-bit transparent D-type latches with 3-state outputs designed for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.