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Technical Specifications
Parameters and characteristics for this part
| Specification | SN65DSI86IPAPQ1 |
|---|---|
| Applications | Tablet, Notebook PC, Netbooks |
| Grade | Automotive |
| Interface | Serial |
| Mounting Type | Surface Mount |
| Package / Case | 64-PowerTQFP |
| Qualification | AEC-Q100 |
| Supplier Device Package | 64-HTQFP (10x10) |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 160 | $ 16.18 | |
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 16.31 | |
| 100 | $ 14.25 | |||
| 250 | $ 10.99 | |||
| 1000 | $ 9.83 | |||
Description
General part information
SN65DSI86-Q1 Series
The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.
The SN65DSI86-Q1 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.
Designed with industry compliant interface technology, the is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.
Documents
Technical documentation and resources
