The AFE77xxD is a pin-compatible family of high-performance, multichannel transceivers, integrating four (AFE7768D/AFE7769D) or two (AFE7728D) direct up-conversion transmitter chains, four (AFE7768D/AFE7769D) or two (AFE7728D) direct down-conversion receiver chains, two wideband RF sampling digitizing auxiliary chains (feedback paths) and low-power Digital Pre-Distortion (DPD) engine for Power Amplifier (PA) linearization. The high dynamic range of the transmitter and receiver chains enables wireless base stations to transmit and receive 2G, 3G, 4G, and 5G signals. The integrated Crest Factor Reduction (CFR) unit helps reduce the Peak-to-Average Ratio (PAR) of the input signal for more efficient transmission through the Power Amplifier. The integrated hardware accelerated DPD estimator and corrector provides flexible and efficient DPD solution for PA linearization. The integrated DPD engine corrects the distortion due to PA nonlinearity for signals up to 200MHz (AFE77x8D) / 300MHz (AFE7769D) instantaneous bandwidth, and within up to 650MHz (AFE77x8D) / 730MHz (AFE7769D) DPD expanded bandwidth. A dedicated GaN corrector addresses the long-term nonlinear memory effects due to charge trapping of GaN PAs.

The low power dissipation and high density channel integration of the AFE77xxD allow the device to address the power and size constraints of 4G and 5G base stations. The wideband and high dynamic range feedback path can assist the DPD of the power amplifiers in the transmitter chain through smart data capture at various intercepting points. The available 29.5Gbps SerDes speed can help reduce the number of lanes required to transfer the data in and out of the device.

Each receiver chain of the AFE77xxD includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated antialiasing low pass filters with programmable bandwidth, driving continuous-time sigma-delta ADCs. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz (AFE77x8D) / 300 MHz (AFE7769D). Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.Read more