Zenode.ai Logo
Beta
16 SOIC
Integrated Circuits (ICs)

SN74LV161AD

Obsolete
Texas Instruments

4-BIT SYNCHRONOUS BINARY COUNTERS

Deep-Dive with AI

Search across all available documentation for this part.

16 SOIC
Integrated Circuits (ICs)

SN74LV161AD

Obsolete
Texas Instruments

4-BIT SYNCHRONOUS BINARY COUNTERS

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LV161AD
Count Rate95 MHz
DirectionUp
Logic TypeBinary Counter
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
ResetAsynchronous
Supplier Device Package16-SOIC
TimingSynchronous
Trigger TypePositive Edge
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.08
10$ 0.96
40$ 0.91
120$ 0.75
280$ 0.70
520$ 0.62
1000$ 0.49
Texas InstrumentsTUBE 1$ 0.80
100$ 0.61
250$ 0.45
1000$ 0.32

Description

General part information

SN74LV161A Series

The ’LV161A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCCoperation.

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.

These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

Documents

Technical documentation and resources