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196-LFBGA
Integrated Circuits (ICs)

DAC3484IZAYR

Active
Texas Instruments

QUAD-CHANNEL, 16-BIT, 1.25-GSPS, 1X-16X INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)

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196-LFBGA
Integrated Circuits (ICs)

DAC3484IZAYR

Active
Texas Instruments

QUAD-CHANNEL, 16-BIT, 1.25-GSPS, 1X-16X INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC)

Technical Specifications

Parameters and characteristics for this part

SpecificationDAC3484IZAYR
ArchitectureCurrent Source
Data InterfaceLVDS - Parallel
Differential OutputTrue
INL/DNL (LSB)4 LSB, 2 LSB
Mounting TypeSurface Mount
Number of Bits16
Number of D/A Converters4
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeCurrent - Unbuffered
Package / Case196-LFBGA
Reference TypeExternal, Internal
Settling Time10 ns
Voltage - Supply, Analog [Max]3.46 V
Voltage - Supply, Analog [Min]3.14 V
Voltage - Supply, Digital [Max]1.32 V
Voltage - Supply, Digital [Min]1.14 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 90.58
10$ 85.91
25$ 83.57
100$ 77.72
Digi-Reel® 1$ 90.58
10$ 85.91
25$ 83.57
100$ 77.72
Tape & Reel (TR) 1000$ 72.33
Texas InstrumentsLARGE T&R 1$ 76.95
100$ 74.64
250$ 62.14
1000$ 57.86

Description

General part information

DAC3484 Series

The DAC3484 is a very low power, high dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS.

The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase and group delay between channels in direct up-conversion applications.

Digital data is input to the device through a 16-bit LVDS data bus with on-chip termination. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.