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TPS65216D0RSLT

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Texas Instruments

INTEGRATED POWER MANAGEMENT (PMIC) FOR ARM® CORTEX™-A8/A9 SOCS AND FPGAS

VQFN (RSL)
Integrated Circuits (ICs)

TPS65216D0RSLT

Active
Texas Instruments

INTEGRATED POWER MANAGEMENT (PMIC) FOR ARM® CORTEX™-A8/A9 SOCS AND FPGAS

Technical Specifications

Parameters and characteristics for this part

SpecificationTPS65216D0RSLT
ApplicationsIndustrial Automation
Current - Supply220 µA
Mounting TypeSurface Mount
Operating Temperature [Max]105 ░C
Operating Temperature [Min]-40 °C
Package / Case48-VFQFN Exposed Pad
Supplier Device Package48-VQFN (6x6)
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]3.6 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 3.34
10$ 3.00
25$ 2.84
100$ 2.46
Digi-Reel® 1$ 3.34
10$ 3.00
25$ 2.84
100$ 2.46
Tape & Reel (TR) 250$ 2.33
500$ 2.09
1250$ 1.76
2500$ 1.68
Texas InstrumentsSMALL T&R 1$ 2.52
100$ 2.21
250$ 1.55
1000$ 1.25

Description

General part information

TPS65216 Series

The TPS65216 is a single chip, power-management IC (PMIC) specifically designed to support the AMIC110, AMIC120, AM335x, and AM437x line of processors in line-powered (5 V) applications. The device is characterized across a –40°C to +105°C temperature range, making it suitable for various industrial applications.

The TPS65216 is specifically designed to provide power management for all the functionalities of the AMIC110, AMIC120, AM335x, and AM437x. The DC/DC converters DCDC1 through DCDC4 are intended to power the core, MPU, DDR memory, and 3.3-V analog and I/O, respectively. LDO1 provides the 1.8-V analog and I/O for the processor. GPIO2 allows for warm reset of the DCDC1 and DCDC2 converters. The I2C interface allows the user to enable and disable all voltage regulators, the load switch, and GPIOs. Additionally, UVLO and supervisor voltage thresholds, power-up sequence, and power-down sequence can be programmed through I2C. Interrupts for overtemperature, overcurrent, and undervoltage can be monitored as well. The supervisor monitors DCDC1 through DCDC4 and LDO1. The supervisor has two settings, one for typical undervoltage tolerance (STRICT = 0b), and one for tight undervoltage and overvoltage tolerances (STRICT = 1b). A power-good signal indicates proper regulation of the five voltage regulators.

Three hysteretic step-down converters are targeted at providing power for the processor core, MPU, and DDRx memory. The default output voltages for each converter can be adjusted through the I2C interface. DCDC1 and DCDC2 feature dynamic voltage scaling to provide power at all operating points of the processor. DCDC1 and DCDC2 also have programmable slew rates to help protect processor components. DCDC3 remains powered while the processor is in sleep mode to maintain power to DDRx memory.