Specification	74LVX161284MTDX

Logic Type	IEEE STD 1284 Translation Transceiver
Mounting Type	Surface Mount
Number of Bits	8
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Package / Case	48-TFSOP
Package / Case	0.24 in
Package / Case [custom]	6.1 mm
Supplier Device Package	48-TSSOP
Supply Voltage [Max]	3.6 V
Supply Voltage [Min]	3 V

74LVX161284 Series

Low Voltage IEEE 161284 Translating Transceiver

Part	Package / Case	Package / Case	Package / Case [custom]	Supply Voltage [Min]	Supply Voltage [Max]	Logic Type	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Number of Bits	Mounting Type	Package / Case [y]	Package / Case [y]
ON Semiconductor 74LVX161284MTD	48-TFSOP	0.24 in	6.1 mm	3 V	3.6 V	IEEE STD 1284 Translation Transceiver	85 °C	-40 °C	48-TSSOP	8	Surface Mount
ON Semiconductor 74LVX161284MTD	48-TFSOP	0.24 in	6.1 mm	3 V	3.6 V	IEEE STD 1284 Translation Transceiver	85 °C	-40 °C	48-TSSOP	8	Surface Mount
ON Semiconductor 74LVX161284MTDX	48-TFSOP	0.24 in	6.1 mm	3 V	3.6 V	IEEE STD 1284 Translation Transceiver	85 °C	-40 °C	48-TSSOP	8	Surface Mount
ON Semiconductor 74LVX161284MEA	48-BSSOP			3 V	3.6 V	IEEE STD 1284 Translation Transceiver	85 °C	-40 °C	48-SSOP	8	Surface Mount	0.295 in	7.5 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 1.56
		10	$ 1.41
		25	$ 1.33
		100	$ 1.06
		250	$ 0.93
		500	$ 0.90

Description

General part information

74LVX161284 Series

The LVX161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA) and are connected to a separate power supply pin (VCC-cable) to allow these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCC-cable supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1-A8/B1-B8transceiver pins.