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16 SO
Integrated Circuits (ICs)

SN74AHCT139NSR

Obsolete
Texas Instruments

IC DECODER/DEMUX 1 X 2:4 16SO

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16 SO
Integrated Circuits (ICs)

SN74AHCT139NSR

Obsolete
Texas Instruments

IC DECODER/DEMUX 1 X 2:4 16SO

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74AHCT139NSR
Circuit1 x 2:4
Current - Output High, Low [custom]8 mA
Current - Output High, Low [custom]8 mA
Independent Circuits2
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case0.209 "
Package / Case16-SOIC
Package / Case5.3 mm
Supplier Device Package16-SO
TypeDecoder/Demultiplexer
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V
Voltage Supply SourceSingle Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

SN74AHCT139 Series

The ’AHCT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V VCCoperation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The ’AHCT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V VCCoperation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Documents

Technical documentation and resources

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