TSB43AA82APGE
Obsolete2-PORT HIGH PERFORMANCE INTEGRATED PHY AND LINK LAYER CHIP FOR PC PERIPHERALS
Deep-Dive with AI
Search across all available documentation for this part.
TSB43AA82APGE
Obsolete2-PORT HIGH PERFORMANCE INTEGRATED PHY AND LINK LAYER CHIP FOR PC PERIPHERALS
Technical Specifications
Parameters and characteristics for this part
| Specification | TSB43AA82APGE |
|---|---|
| Function | Physical Layer Controller |
| Interface | Parallel |
| Package / Case | 144-LQFP |
| Protocol | IEEE 1394 |
| Standards | IEEE 1394a-2000 |
| Supplier Device Package | 144-LQFP (20x20) |
| Voltage - Supply | 3.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 15.67 | |
| 100 | $ 13.69 | |||
| 250 | $ 10.55 | |||
| 1000 | $ 9.44 | |||
Description
General part information
TSB43AA82A Series
The TSB43AA82A is a high performance 1394 integrated PHY and link layer controller. It is compliant with the IEEE 1394-1995 and IEEE1394.a-2000 specifications and supports asynchronous transfers.
The TSB43AA82A has a generic 16/8-bit host bus interface. It supports parallel or multiplexed connections to the microcontroller (MCU) at rates up to 40 MHz.
The TSB43AA82A offers large data transfers with three mutually independent FIFOs: 1) the asynchronous command FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504 bytes.
Documents
Technical documentation and resources