SN74ALVCH16721DGGR
Active3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
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SN74ALVCH16721DGGR
Active3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVCH16721DGGR |
|---|---|
| Clock Frequency | 150 MHz |
| Current - Output High, Low | 24 mA |
| Function | Standard |
| Input Capacitance | 3.5 pF |
| Max Propagation Delay @ V, Max CL | 4.3 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 20 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 6.1 mm |
| Package / Case | 0.24 in |
| Package / Case | 56-TFSOP |
| Supplier Device Package | 56-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.11 | |
| 10 | $ 1.89 | |||
| 25 | $ 1.79 | |||
| 100 | $ 1.52 | |||
| 250 | $ 1.43 | |||
| 500 | $ 1.25 | |||
| 1000 | $ 1.04 | |||
| Digi-Reel® | 1 | $ 2.11 | ||
| 10 | $ 1.89 | |||
| 25 | $ 1.79 | |||
| 100 | $ 1.52 | |||
| 250 | $ 1.43 | |||
| 500 | $ 1.25 | |||
| 1000 | $ 1.04 | |||
| Tape & Reel (TR) | 2000 | $ 0.96 | ||
| 6000 | $ 0.93 | |||
| 10000 | $ 0.89 | |||
| Texas Instruments | LARGE T&R | 1 | $ 1.58 | |
| 100 | $ 1.31 | |||
| 250 | $ 0.94 | |||
| 1000 | $ 0.71 | |||
Description
General part information
SN74ALVCH16721 Series
This 20-bit flip-flop is designed specifically for 1.65-V to 3.6-V VCCoperation.
The 20 flip-flops of the SN74ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored.
A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Documents
Technical documentation and resources
