Deep-Dive with AI
Search across all available documentation for this part.
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALS992DWRG4 |
|---|---|
| Circuit | 9 |
| Current - Output High, Low [custom] | 400 µA |
| Current - Output High, Low [custom] | 8 mA |
| Delay Time - Propagation | 6 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Tri-State |
| Package / Case | 24-SOIC |
| Package / Case [custom] | 7.5 mm |
| Package / Case [custom] | 0.295 in |
| Supplier Device Package | 24-SOIC |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74ALS992 Series
This 9-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. In addition, this device provides a 3-state buffer-type output and is easily implemented in parity applications.
The nine latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. The Q outputs are in the 3-state condition when the output-enable () input is high.
Read back is provided through the output-enable () input. Whenis taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. Whenis taken high, the output of the data latches is isolated from the D inputs.does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict.
Documents
Technical documentation and resources
No documents available
