Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Logic Type	Operating Temperature [Min]	Operating Temperature [Max]	Delay Time - Propagation	Circuit [custom]	Circuit [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Output Type	Package / Case	Mounting Type	Independent Circuits	Supplier Device Package
Texas Instruments JM38510/65403BRA	7.8 mA	7.8 mA	D-Type Transparent Latch	-55 °C	125 °C	20 ns	8	8	2 V	6 V	Non-Inverted Tri-State	20-CDIP	Through Hole	1	20-CDIP
Texas Instruments JM38510/65403B2A	7.8 mA	7.8 mA	D-Type Transparent Latch	-55 °C	125 °C	20 ns	8	8	2 V	6 V	Non-Inverted Tri-State	20-CLCC	Surface Mount	1	20-LCCC (8.89x8.89)
Texas Instruments 84072012A

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Bulk	8	$ 38.66
		9	$ 36.52
Texas Instruments	TUBE	1	$ 51.09
		100	$ 44.62
		250	$ 34.41
		1000	$ 30.77

Description

General part information

SN54HC373 Series

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

Documents

Technical documentation and resources

SNx4HC373 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. G)

Data sheet

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

SN54/74HCT CMOS Logic Family Applications and Restrictions

Application note

Logic Guide (Rev. AB)

Selection guide

Signal Switch Data Book (Rev. A)

User guide

84072012A

Deep-Dive with AI

84072012A

Deep-Dive with AI

Technical Specifications

SN54HC373 Series

Pricing

Description

SN54HC373 Series

Documents

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

LOGIC Pocket Data Book (Rev. B)

Designing With Logic (Rev. C)

Input and Output Characteristics of Digital Integrated Circuits

Power-Up Behavior of Clocked Devices (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Live Insertion

TI IBIS File Creation, Validation, and Distribution Processes

CMOS Power Consumption and CPD Calculation (Rev. B)

SNx4HC373 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. G)

Implications of Slow or Floating CMOS Inputs (Rev. E)

SN54/74HCT CMOS Logic Family Applications and Restrictions

Logic Guide (Rev. AB)

Signal Switch Data Book (Rev. A)

SN54HC373 Series