CD54HCT174F
ActiveHIGH SPEED CMOS LOGIC HEX D-TYPE FLIP-FLOPS WITH RESET
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CD54HCT174F
ActiveHIGH SPEED CMOS LOGIC HEX D-TYPE FLIP-FLOPS WITH RESET
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HCT174F |
|---|---|
| Clock Frequency | 25 MHz |
| Current - Output High, Low [custom] | 4 mA |
| Current - Output High, Low [custom] | 4 mA |
| Current - Quiescent (Iq) | 8 ÁA |
| Input Capacitance | 10 pF |
| Max Propagation Delay @ V, Max CL | 40 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 6 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Non-Inverted |
| Package / Case | 7.62 mm, 0.3 in |
| Package / Case | 16-CDIP |
| Supplier Device Package | 16-CDIP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 21.80 | |
| 100 | $ 19.04 | |||
| 250 | $ 14.68 | |||
| 1000 | $ 13.13 | |||
Description
General part information
CD54HCT174 Series
The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state.
Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.
The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state.
Documents
Technical documentation and resources