Specification	NLV14001UBDR2G

Current - Output High, Low [custom]	8.8 mA
Current - Output High, Low [custom]	3.5 mA
Current - Quiescent (Max) [Max]	1 çA
Input Logic Level - High [Max]	12.5 V
Input Logic Level - High [Min]	4 V
Input Logic Level - Low [Max]	2.5 V
Input Logic Level - Low [Min]	1 V
Logic Type	NOR Gate
Max Propagation Delay @ V, Max CL	80 ns
Mounting Type	Surface Mount
Number of Circuits	4
Number of Inputs	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Package / Case	14-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Voltage - Supply [Max]	18 V
Voltage - Supply [Min]	3 V

MC14001UB Series

Quad 2-Input NOR Gate

Part	Package / Case [x]	Package / Case [y]	Package / Case	Logic Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Input Logic Level - Low [Max]	Input Logic Level - Low [Min]	Number of Circuits	Input Logic Level - High [Max]	Input Logic Level - High [Min]	Max Propagation Delay @ V, Max CL	Number of Inputs	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Quiescent (Max) [Max]
ON Semiconductor NLV14001BCP
ON Semiconductor NLV14001UBDR2G	0.154 in	3.9 mm	14-SOIC	NOR Gate	18 V	3 V	2.5 V	1 V	4	12.5 V	4 V	80 ns	2	-55 °C	125 °C	Surface Mount	8.8 mA	3.5 mA	1 çA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	2500	$ 0.21
		5000	$ 0.21
		12500	$ 0.20
		25000	$ 0.20
LCSC	Piece	1	$ 0.49
		200	$ 0.19
		500	$ 0.18
		1000	$ 0.18
Newark	Each (Supplied on Full Reel)	1	$ 0.27
		3000	$ 0.26
		6000	$ 0.24
		12000	$ 0.23
		18000	$ 0.21
		30000	$ 0.20
ON Semiconductor	N/A	1	$ 0.21

Description

General part information

MC14001UB Series

The UB Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. The UB set of CMOS gates are inverting non-buffered functions.