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56-TSSOP
Integrated Circuits (ICs)

SN74ALVCH162721DLR

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Texas Instruments

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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56-TSSOP
Integrated Circuits (ICs)

SN74ALVCH162721DLR

Active
Texas Instruments

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ALVCH162721DLR
Clock Frequency150 MHz
Current - Output High, Low [custom]12 mA
Current - Output High, Low [custom]12 mA
FunctionStandard
Input Capacitance3.5 pF
Mounting TypeSurface Mount
Number of Bits per Element20
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State, Non-Inverted
Package / Case0.295 in
Package / Case56-BSSOP
Package / Case7.5 mm
Supplier Device Package56-SSOP
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 4.48
Digi-Reel® 1$ 4.48
Tape & Reel (TR) 1000$ 2.37
2000$ 2.25
Texas InstrumentsLARGE T&R 1$ 3.38
100$ 2.96
250$ 2.08
1000$ 1.67

Description

General part information

SN74ALVCH162721 Series

This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCCoperation.

The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored.

A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.