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32-LQFP
Integrated Circuits (ICs)

MC100EP131FAR2G

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ON Semiconductor

QUAD D FLIP-FLOP WITH SET, RESET, AND DIFFERENTIAL CLOCK

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32-LQFP
Integrated Circuits (ICs)

MC100EP131FAR2G

Active
ON Semiconductor

QUAD D FLIP-FLOP WITH SET, RESET, AND DIFFERENTIAL CLOCK

Technical Specifications

Parameters and characteristics for this part

SpecificationMC100EP131FAR2G
Clock Frequency3 GHz
Current - Quiescent (Iq)120 mA
FunctionReset, Set(Preset)
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case32-LQFP
Supplier Device Package32-LQFP (7x7)
Trigger TypeNegative, Positive
TypeD-Type
Voltage - Supply [Max]-5.5 V
Voltage - Supply [Min]-3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 22.00
10$ 20.29
25$ 19.38
100$ 16.53
250$ 15.73
500$ 14.59
Digi-Reel® 1$ 22.00
10$ 20.29
25$ 19.38
100$ 16.53
250$ 15.73
500$ 14.59
Tape & Reel (TR) 2000$ 14.11
NewarkEach (Supplied on Full Reel) 1200$ 13.43

Description

General part information

MC100EP131 Series

The MC10EP131 is a Quad Master-slaved D flip-flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available.Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and (CCbar) HIGH, then using the Clock Enable inputs for clocking (C0-3and C0-3bar).Common clocking is achieved by holding the C0-3inputs LOW and C0-3bar inputs HIGH while using the differential common clock CCto clock all four flip-flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state.Individual asynchronous resets (R0-3) and an asynchronous set (SET) are provided.Data enters the master when both CCand C0-3are LOW, and transfers to the slave when either CCor C0-3(or both) go HIGH.The 100 Series contains temperature compensation.