Zenode.ai Logo
Beta
24-pin (DW) package image
Integrated Circuits (ICs)

CD74HC4059M96

Active
Texas Instruments

HIGH SPEED CMOS LOGIC CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER

Deep-Dive with AI

Search across all available documentation for this part.

24-pin (DW) package image
Integrated Circuits (ICs)

CD74HC4059M96

Active
Texas Instruments

HIGH SPEED CMOS LOGIC CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74HC4059M96
Count Rate32 MHz
DirectionDown
Logic TypeDivide-by-N
Mounting TypeSurface Mount
Number of Bits per Element16
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case24-SOIC
Package / Case [custom]7.5 mm
Package / Case [custom]0.295 in
ResetAsynchronous
Supplier Device Package24-SOIC
TimingSynchronous
Trigger TypePositive Edge
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 2.88
10$ 2.59
25$ 2.45
100$ 2.12
250$ 2.01
500$ 1.81
1000$ 1.52
Digi-Reel® 1$ 2.88
10$ 2.59
25$ 2.45
100$ 2.12
250$ 2.01
500$ 1.81
1000$ 1.52
Tape & Reel (TR) 2000$ 1.45
6000$ 1.39
Texas InstrumentsLARGE T&R 1$ 2.39
100$ 2.10
250$ 1.47
1000$ 1.19

Description

General part information

CD74HC4059 Series

The ’HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number "N" from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-counter is preset by means of 16 jam inputs.

The three Mode-Select Inputs Ka,Kband Kcdetermine the modulus ("divide-by" number) of the first and last counting sections in accordance with the truth table. Every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section an the last counting section, which consists of flip-flops that are not needed for opening the first counting section. For example, in the10) counters presettable by means of Jam Inputs J5 through J16.

The Mode-Select Inputs permit frequency-synthesizer channel separations of 10, 12.5, 20, 25 or 50 parts. These inputs set the maximum value of N at 9999 (when the first counting section divides by 5 or 10) or 15,999 (when the first counting section divides by 8, 4, or 2).

Documents

Technical documentation and resources