
MC74HC393ADTR2G
ActiveIC,COUNTER,UP,4-BIT BINARY,HC-CMOS,TSSOP,14PIN,PLASTIC
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MC74HC393ADTR2G
ActiveIC,COUNTER,UP,4-BIT BINARY,HC-CMOS,TSSOP,14PIN,PLASTIC
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC74HC393ADTR2G |
|---|---|
| Count Rate | 50 MHz |
| Direction | Up |
| Logic Type | Binary Counter |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 4 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 14-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Reset | Asynchronous |
| Supplier Device Package | 14-TSSOP |
| Trigger Type | Negative Edge |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.15 | |
| 10 | $ 0.68 | |||
| 25 | $ 0.57 | |||
| 100 | $ 0.44 | |||
| 250 | $ 0.38 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.31 | |||
| Digi-Reel® | 1 | $ 1.15 | ||
| 10 | $ 0.68 | |||
| 25 | $ 0.57 | |||
| 100 | $ 0.44 | |||
| 250 | $ 0.38 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.31 | |||
| Tape & Reel (TR) | 2500 | $ 0.28 | ||
| 5000 | $ 0.26 | |||
| 7500 | $ 0.25 | |||
| 12500 | $ 0.24 | |||
| 17500 | $ 0.24 | |||
| 25000 | $ 0.23 | |||
| Newark | Each (Supplied on Full Reel) | 1 | $ 0.32 | |
| 3000 | $ 0.31 | |||
| 6000 | $ 0.28 | |||
| 12000 | $ 0.27 | |||
| 18000 | $ 0.25 | |||
| 30000 | $ 0.24 | |||
| ON Semiconductor | N/A | 1 | $ 0.25 | |
Description
General part information
MC74HC393A Series
High-Performance Silicon-Gate CMOSThe MC74HC393A is identical in pinout to the LS393. The device inputs are compatible with standard CMOS outputs; with pullup resistors,they are compatible with LSTTL outputs.This device consists of two independent 4-bit binary ripple counters with parallel outputs from each counter stage. A divide-by 256 counter can be obtained by cascading the two binary counters.Internal flip-flops are triggered by high-to-low transitions of the clock input. Reset for the counters is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the HC393A.
Documents
Technical documentation and resources