Specification	CD54HC4046AF

Differential - Input:Output	False
Divider/Multiplier	False
Frequency - Max [Max]	38 MHz
Input	CMOS
Mounting Type	Through Hole
Number of Circuits	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output	CMOS
Package / Case	7.62 mm, 0.3 in
Package / Case	16-CDIP
PLL	True
Ratio - Input:Output	1:4
Supplier Device Package	16-CDIP
Type	Phase Lock Loop (PLL)
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

CD54HC4046A Series

High Speed CMOS Logic Phase-Locked-Loop with VCO

Part	Number of Circuits	Package / Case	Package / Case	Differential - Input:Output	Output	Type	Operating Temperature [Max]	Operating Temperature [Min]	Ratio - Input:Output	PLL	Divider/Multiplier	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Input	Frequency - Max [Max]
Texas Instruments CD54HC4046AF3A	1	0.3 in 7.62 mm	16-CDIP		CMOS	Phase Lock Loop (PLL)	125 °C	-55 °C	1:4			Through Hole	2 V	6 V	16-CDIP	CMOS	38 MHz
Texas Instruments CD54HC4046AF	1	0.3 in 7.62 mm	16-CDIP		CMOS	Phase Lock Loop (PLL)	125 °C	-55 °C	1:4			Through Hole	2 V	6 V	16-CDIP	CMOS	38 MHz

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	TUBE	1	$ 29.90
		100	$ 26.58
		250	$ 21.85
		1000	$ 19.54

Description

General part information

CD54HC4046A Series

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

Documents

Technical documentation and resources

Datasheet

CD54HC4046AF

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CD54HC4046AF

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Technical Specifications

CD54HC4046A Series

Pricing

Description

CD54HC4046A Series

Documents

Datasheet

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

LOGIC Pocket Data Book (Rev. B)

Signal Switch Data Book (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Implications of Slow or Floating CMOS Inputs (Rev. E)

TI IBIS File Creation, Validation, and Distribution Processes

Logic Guide (Rev. AB)

Live Insertion

SN54/74HCT CMOS Logic Family Applications and Restrictions

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

CMOS Phase-Locked-Loop Applications (Rev. B)

Implementation of FSK Modulation and Demodulation using CD74HC4046A

CMOS Power Consumption and CPD Calculation (Rev. B)

Designing With Logic (Rev. C)

Input and Output Characteristics of Digital Integrated Circuits

CD54HC4046A Series