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24-SOIC
Integrated Circuits (ICs)

SN74BCT652DWR

Unknown
Texas Instruments

IC TXRX NON-INVERT 5.5V 24SOIC

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24-SOIC
Integrated Circuits (ICs)

SN74BCT652DWR

Unknown
Texas Instruments

IC TXRX NON-INVERT 5.5V 24SOIC

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74BCT652DWR
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]15 mA
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output Type3-State
Package / Case24-SOIC
Package / Case [custom]7.5 mm
Package / Case [custom]0.295 in
Supplier Device Package24-SOIC
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 10.10
Digi-Reel® 1$ 10.10
Tape & Reel (TR) 2000$ 5.51

Description

General part information

SN74BCT652 Series

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.

Output-enable (OEAB and) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ´BCT652.

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and. In this configuration each output reinforces its input. Therefore, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remain at its last state.

Documents

Technical documentation and resources

No documents available