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TSSOP (PW)
Integrated Circuits (ICs)

CD74HC192PWT

Obsolete
Texas Instruments

HIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS BCD DECADE UP/DOWN COUNTER WITH ASYNCHRONOUS RESET

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TSSOP (PW)
Integrated Circuits (ICs)

CD74HC192PWT

Obsolete
Texas Instruments

HIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS BCD DECADE UP/DOWN COUNTER WITH ASYNCHRONOUS RESET

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74HC192PWT
Count Rate24 MHz
DirectionUp, Down
Logic TypeCounter, Decade
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
ResetAsynchronous
Supplier Device Package16-TSSOP
TimingSynchronous
Trigger TypePositive Edge
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

CD74HC192 Series

High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter with Asynchronous Reset

PartSupplier Device PackageNumber of ElementsVoltage - Supply [Min]Voltage - Supply [Max]TimingOperating Temperature [Min]Operating Temperature [Max]Trigger TypePackage / Case [x]Package / CasePackage / Case [y]Number of Bits per ElementCount RateLogic TypeDirectionMounting TypeResetPackage / CasePackage / Case
16-TSSOP
Texas Instruments
16-TSSOP
1
2 V
6 V
Synchronous
-55 °C
125 °C
Positive Edge
0.173 in
16-TSSOP
4.4 mm
4
24 MHz
Counter
Decade
Down
Up
Surface Mount
Asynchronous
16-TSSOP
Texas Instruments
16-TSSOP
1
2 V
6 V
Synchronous
-55 °C
125 °C
Positive Edge
0.173 in
16-TSSOP
4.4 mm
4
24 MHz
Counter
Decade
Down
Up
Surface Mount
Asynchronous
TSSOP (PW)
Texas Instruments
16-TSSOP
1
2 V
6 V
Synchronous
-55 °C
125 °C
Positive Edge
0.173 in
16-TSSOP
4.4 mm
4
24 MHz
Counter
Decade
Down
Up
Surface Mount
Asynchronous
PDIP (N)
Texas Instruments
16-PDIP
1
2 V
6 V
Synchronous
-55 °C
125 °C
Positive Edge
16-DIP
4
24 MHz
Counter
Decade
Down
Up
Through Hole
Asynchronous
0.3 in
7.62 mm
Product Image
Texas Instruments
16-SO
1
2 V
6 V
Synchronous
-55 °C
125 °C
Positive Edge
16-SOIC
4
24 MHz
Counter
Decade
Down
Up
Surface Mount
Asynchronous
0.209 "
5.3 mm
16-TSSOP
Texas Instruments
16-TSSOP
1
2 V
6 V
Synchronous
-55 °C
125 °C
Positive Edge
0.173 in
16-TSSOP
4.4 mm
4
24 MHz
Counter
Decade
Down
Up
Surface Mount
Asynchronous
16-SO
Texas Instruments
16-SO
1
2 V
6 V
Synchronous
-55 °C
125 °C
Positive Edge
16-SOIC
4
24 MHz
Counter
Decade
Down
Up
Surface Mount
Asynchronous
0.209 "
5.3 mm
16-TSSOP
Texas Instruments
16-TSSOP
1
2 V
6 V
Synchronous
-55 °C
125 °C
Positive Edge
0.173 in
16-TSSOP
4.4 mm
4
24 MHz
Counter
Decade
Down
Up
Surface Mount
Asynchronous

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 2.14
10$ 1.37
25$ 1.16
100$ 0.94
Digi-Reel® 1$ 1.45
10$ 1.30
25$ 1.23
100$ 1.01
Tape & Reel (TR) 250$ 0.95
500$ 0.84
1250$ 0.66
2500$ 0.62
6250$ 0.59
12500$ 0.56
Texas InstrumentsSMALL T&R 1$ 1.08
100$ 0.83
250$ 0.61
1000$ 0.44

Description

General part information

CD74HC192 Series

The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.

Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.

If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.