ADC3223IRGZT
ActiveDUAL-CHANNEL, 12-BIT, 80-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)
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ADC3223IRGZT
ActiveDUAL-CHANNEL, 12-BIT, 80-MSPS ANALOG-TO-DIGITAL CONVERTER (ADC)
Technical Specifications
Parameters and characteristics for this part
| Specification | ADC3223IRGZT |
|---|---|
| Architecture | Pipelined |
| Configuration | ADC |
| Data Interface | LVDS - Serial |
| Features | Simultaneous Sampling |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 2 |
| Number of Bits | 12 bits |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 48-VFQFN Exposed Pad |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 80 M |
| Supplier Device Package | 48-VQFN (7x7) |
| Voltage - Supply, Analog [Max] | 1.9 V |
| Voltage - Supply, Analog [Min] | 1.7 V |
| Voltage - Supply, Digital [Max] | 1.9 V |
| Voltage - Supply, Digital [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 250 | $ 25.75 | |
| Texas Instruments | SMALL T&R | 1 | $ 26.91 | |
| 100 | $ 23.92 | |||
| 250 | $ 19.66 | |||
| 1000 | $ 17.59 | |||
Description
General part information
ADC3223 Series
The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
Documents
Technical documentation and resources
