CD54HC190F3A
ActiveHIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS 4-BIT BCD DECADE UP/DOWN COUNTER
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CD54HC190F3A
ActiveHIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS 4-BIT BCD DECADE UP/DOWN COUNTER
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HC190F3A |
|---|---|
| Count Rate | 35 MHz |
| Direction | Up, Down |
| Logic Type | BCD Counter, Decade |
| Mounting Type | Through Hole |
| Number of Bits per Element | 4 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 7.62 mm, 0.3 in |
| Package / Case | 16-CDIP |
| Reset | Asynchronous |
| Supplier Device Package | 16-CDIP |
| Timing | Synchronous |
| Trigger Type | Positive Edge |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 27.56 | |
| 100 | $ 24.50 | |||
| 250 | $ 20.14 | |||
| 1000 | $ 18.01 | |||
Description
General part information
CD54HC190 Series
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).
Documents
Technical documentation and resources