Development Boards, Kits, Programmers

ADC12D1600RB/NOPB

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Texas Instruments

REFERENCE BOARD, VIRTEX-4 FPGA, ADC

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DocumentsOperating Instructions EN Datasheet

Development Boards, Kits, Programmers

ADC12D1600RB/NOPB

Active

Texas Instruments

REFERENCE BOARD, VIRTEX-4 FPGA, ADC

Deep-Dive with AI

DocumentsOperating Instructions EN Datasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	ADC12D1600RB/NOPB

Data Interface	SPI, LVDS, Serial
Input Range	800 mVpp
Number of A/D Converters	2
Number of Bits	12 bits
Power (Typ) @ Conditions	3.88 W
Sampling Rate (Per Second)	3.2 G
Supplied Contents	Cable(s), Power Supply, Board(s)
Utilized IC / Part	ADC12D1600

ADC12DJ3200 Series

12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)

Part	Utilized IC / Part	Sampling Rate (Per Second)	Supplied Contents	Number of Bits	Power (Typ) @ Conditions	Number of A/D Converters	Data Interface	Input Range	Features	Supplier Device Package	Number of Inputs	Ratio - S/H:ADC	Input Type	Mounting Type	Configuration	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Architecture	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Reference Type	Package / Case
Texas Instruments ADC12J1600EVM	ADC12J1600	1.6 G	Board(s)	12 bits	1.59 W	1	JESD204B Serial
Texas Instruments ADC12DL3200EVM	ADC12DL3200	3.2 G 6.4 G	Board(s) Cable(s)	12 bits		2	LVDS - Parallel	1 Vpp
Texas Instruments ADC12D1600RB/NOPB	ADC12D1600	3.2 G	Board(s) Cable(s) Power Supply	12 bits	3.88 W	2	LVDS Serial SPI	800 mVpp
Texas Instruments ADC12DJ3200ZEGT		3.2 G 6.4 G		12 bits		2	JESD204B		Simultaneous Sampling	144-FCBGA	1 2	0:1	Differential Single Ended	Surface Mount	MUX-ADC	1.15 V	1.05 V	Flash	85 °C	-40 °C	1.05 V 1.8 V	1.15 V 2 V	Internal
Texas Instruments ADC12DJ3200ZEG		3.2 G 6.4 G		12 bits		2	JESD204B		Simultaneous Sampling	144-FCBGA	1 2	0:1	Differential Single Ended	Surface Mount	MUX-ADC	1.15 V	1.05 V	Flash	85 °C	-40 °C	1.05 V 1.8 V	1.15 V 2 V	Internal
Texas Instruments ADC12D800RFRB/NOPB		1.6 G	Board(s) Cable(s) Power Supply	12 bits		2	LVDS Serial SPI	800 mVpp
Texas Instruments ADC12DJ3200EVM		6.4 G	Board(s)	12 bits		1	Serial
Texas Instruments ADC12J4000EVM	ADC12J4000	4 G	Board(s) Cable(s) Power Supply	12 bits	2.17 W	1	JESD204B Serial	725 mVpp
Texas Instruments ADC12DJ3200AAV		3.2 G		12 bits		2	JESD204B		Simultaneous Sampling	144-FCBGA (10x10)	1 2	0:1	Differential Single Ended	Surface Mount	MUX-ADC	1.15 V	1.05 V	Flash	85 °C	-40 °C	1.05 V 1.8 V	1.15 V 2 V	Internal	144-FBGA FCBGA
Texas Instruments ADC12D1600RFRB/NOPB	ADC12D1600RF	3.2 G	Board(s) Cable(s) Power Supply	12 bits		2	LVDS Serial SPI	800 mVpp

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Box	1	$ 2398.80
Newark	Each	1	$ 2620.63
		10	$ 2559.21

Description

General part information

ADC12DJ3200 Series

The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

Documents

Technical documentation and resources

Operating Instructions EN

Datasheet