CDC516DGG
Active3.3-V PHASE LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
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CDC516DGG
Active3.3-V PHASE LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | CDC516DGG |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | False |
| Frequency - Max [Max] | 125 MHz |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | LVTTL |
| Package / Case | 48-TFSOP |
| Package / Case | 0.24 in |
| Package / Case [custom] | 6.1 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output | 1:16 |
| Supplier Device Package | 48-TSSOP |
| Type | PLL Clock Driver |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 80 | $ 11.12 | |
| Texas Instruments | TUBE | 1 | $ 12.43 | |
| 100 | $ 10.13 | |||
| 250 | $ 7.96 | |||
| 1000 | $ 6.75 | |||
Description
General part information
CDC516 Series
The CDC516 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC516 operates at 3.3-V VCCand is designed to drive up to five clock loads per output.
Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Documents
Technical documentation and resources
