Specification	SNJ54HC175J

Clock Frequency	60 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	8 ÁA
Input Capacitance	3 pF
Max Propagation Delay @ V, Max CL	26 ns
Mounting Type	Through Hole
Number of Bits per Element	4
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Complementary
Package / Case	7.62 mm, 0.3 in
Package / Case	16-CDIP
Supplier Device Package	16-CDIP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

SN54HC175 Series

Quadruple D-type Flip-Flops With Clear

Part	Output Type	Trigger Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Max Propagation Delay @ V, Max CL	Mounting Type	Number of Bits per Element	Clock Frequency	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case	Current - Quiescent (Iq)	Type	Operating Temperature [Max]	Operating Temperature [Min]	Number of Elements	Input Capacitance
Texas Instruments SNJ54HC175J	Complementary	Positive Edge	5.2 mA	5.2 mA	26 ns	Through Hole	4	60 MHz	16-CDIP	2 V	6 V	0.3 in 7.62 mm	16-CDIP	8 ÁA	D-Type	125 °C	-55 °C	1	3 pF
Texas Instruments JM38510/65308BEA	Complementary	Positive Edge	5.2 mA	5.2 mA	26 ns	Through Hole	4	60 MHz	16-CDIP	2 V	6 V	0.3 in 7.62 mm	16-CDIP	8 ÁA	D-Type	125 °C	-55 °C	1	3 pF
Texas Instruments 8408901EA	Complementary	Positive Edge	5.2 mA	5.2 mA	26 ns	Through Hole	4	60 MHz	16-CDIP	2 V	6 V	0.3 in 7.62 mm	16-CDIP	8 ÁA	D-Type	125 °C	-55 °C	1	3 pF
Texas Instruments 8408901FA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	TUBE	1	$ 14.59
		100	$ 12.74
		250	$ 9.82
		1000	$ 8.79

Description

General part information

SN54HC175 Series

These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature complementary outputs from each flip-flop.

Documents

Technical documentation and resources

SNJ54HC175J

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SNJ54HC175J

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Technical Specifications

SN54HC175 Series

Pricing

Description

SN54HC175 Series

Documents

Live Insertion

Designing With Logic (Rev. C)

CMOS Power Consumption and CPD Calculation (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Implications of Slow or Floating CMOS Inputs (Rev. E)

LOGIC Pocket Data Book (Rev. B)

Logic Guide (Rev. AB)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

SNx4HC175 Quadruple D-Type Flip-Flops With Clear datasheet (Rev. F)

SN54/74HCT CMOS Logic Family Applications and Restrictions

Signal Switch Data Book (Rev. A)

Input and Output Characteristics of Digital Integrated Circuits

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Power-Up Behavior of Clocked Devices (Rev. B)

SN54HC175 Series