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Technical Specifications
Parameters and characteristics for this part
| Specification | DS90UR910QEVM |
|---|---|
| Contents | Board(s) |
| Function | Deserializer |
| Secondary Attributes | SMA Connectors |
| Supplied Contents | Board(s) |
| Type | Interface |
| Utilized IC / Part | DS90UR910Q |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Box | 1 | $ 478.80 | |
Description
General part information
DS90UR910-Q1 Series
The DS90UR910-Q1 is an interface bridge chip that recovers data from the FPD-Link II serial bit stream and converts into a Camera Serial Interface (CSI-2) format compatible with Mobile Industry Processor Interface (MIPI) specifications. It recovers the 24- or 18-bit RGB data and 3 video sync-signals from the serial bit stream compatible to FPD-Link II serializers. The recovered data is packetized and serialized over two data lanes strobed by a half-rate serial clock compliant with the MIPI DPHY and CSI-2 specifications, each running up to 900 Mbps. The FPD-Link II receiver supports pixel clocks of up to75 MHz. The CSI-2 output serial bus greatly reduces the interconnect and signal count to a graphic processing unit (GPU) and eases system designs for video streams from multiple automotive driver assist cameras.
The DS90UR910-Q1 is available in a 40-pin WQFN package. Electrical performance is qualified for automotive AEC-Q100 grade 2 temperature range–40°C to 105°C.
The DS90UR910-Q1 is an interface bridge chip that recovers data from the FPD-Link II serial bit stream and converts into a Camera Serial Interface (CSI-2) format compatible with Mobile Industry Processor Interface (MIPI) specifications. It recovers the 24- or 18-bit RGB data and 3 video sync-signals from the serial bit stream compatible to FPD-Link II serializers. The recovered data is packetized and serialized over two data lanes strobed by a half-rate serial clock compliant with the MIPI DPHY and CSI-2 specifications, each running up to 900 Mbps. The FPD-Link II receiver supports pixel clocks of up to75 MHz. The CSI-2 output serial bus greatly reduces the interconnect and signal count to a graphic processing unit (GPU) and eases system designs for video streams from multiple automotive driver assist cameras.
Documents
Technical documentation and resources