Integrated Circuits (ICs)

SN74AHC74N

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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Search across all available documentation for this part.

DocumentsDesign Summary for WCSP Little Logic (Rev. B)Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)+19

Integrated Circuits (ICs)

SN74AHC74N

Active

Texas Instruments

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

Deep-Dive with AI

DocumentsDesign Summary for WCSP Little Logic (Rev. B)Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)+19

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74AHC74N

Clock Frequency	115 MHz
Current - Output High, Low [custom]	8 mA
Current - Output High, Low [custom]	8 mA
Current - Quiescent (Iq)	2 µA
Function	Reset, Set(Preset)
Input Capacitance	2 pF
Max Propagation Delay @ V, Max CL	9.3 ns
Mounting Type	Through Hole
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	14-DIP
Package / Case [x]	0.3 "
Package / Case [y]	7.62 mm
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	2 V

SN74AHC74Q-Q1 Series

Automotive, catalog dual positive-edge-triggered D-type flip-flops with clear and preset

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Operating Temperature [Min]	Operating Temperature [Max]	Output Type	Function	Mounting Type	Input Capacitance	Max Propagation Delay @ V, Max CL	Voltage - Supply [Max]	Voltage - Supply [Min]	Trigger Type	Current - Quiescent (Iq)	Number of Elements	Package / Case	Package / Case [y]	Package / Case [x]	Type	Clock Frequency	Number of Bits per Element	Supplier Device Package	Package / Case [custom]	Package / Case [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Qualification	Grade
Texas Instruments SN74AHC74N	8 mA	8 mA	-40 °C	125 °C	Complementary	Reset Set(Preset)	Through Hole	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-DIP	7.62 mm	0.3 "	D-Type	115 MHz	1
Texas Instruments SN74AHC74RGYR	8 mA	8 mA	-40 °C	125 °C	Complementary	Reset Set(Preset)	Surface Mount	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-VFQFN Exposed Pad			D-Type	115 MHz	1	14-VQFN (3.5x3.5)
Texas Instruments SN74AHC74MPWREP	8 mA	8 mA			Complementary	Reset Set(Preset)	Surface Mount	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-TSSOP			D-Type	115 MHz	1	14-TSSOP	0.173 "	4.4 mm	125 °C	-55 °C
Texas Instruments SN74AHC74DBR	8 mA	8 mA	-40 °C	125 °C	Complementary	Reset Set(Preset)	Surface Mount	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-SSOP			D-Type	115 MHz	1	14-SSOP					5.3 mm	0.209 "
Texas Instruments SN74AHC74QPWRG4Q1	8 mA	8 mA	-40 °C	125 °C	Complementary	Reset Set(Preset)	Surface Mount	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-TSSOP			D-Type	115 MHz	1	14-TSSOP	0.173 "	4.4 mm					AEC-Q100	Automotive
Texas Instruments SN74AHC74DGVR	8 mA	8 mA	-40 °C	125 °C	Complementary	Reset Set(Preset)	Surface Mount	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-TFSOP		0.173 in 4.4 mm	D-Type	115 MHz	1
Texas Instruments SN74AHC74MDREP	8 mA	8 mA			Complementary	Reset Set(Preset)	Surface Mount	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-SOIC	3.9 mm	0.154 in	D-Type	115 MHz	1				125 °C	-55 °C
Texas Instruments SN74AHC74D	8 mA	8 mA	-40 °C	125 °C	Complementary	Reset Set(Preset)	Surface Mount	2 pF	6.1 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-SOIC	3.9 mm	0.154 in	D-Type	115 MHz	1
Texas Instruments SN74AHC74PWRG4	8 mA	8 mA	-40 °C	125 °C	Complementary	Reset Set(Preset)	Surface Mount	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-TSSOP			D-Type	115 MHz	1	14-TSSOP	0.173 "	4.4 mm
Texas Instruments SN74AHC74PWR	8 mA	8 mA	-40 °C	125 °C	Complementary	Reset Set(Preset)	Surface Mount	2 pF	9.3 ns	5.5 V	2 V	Positive Edge	2 µA	2	14-TSSOP			D-Type	115 MHz	1	14-TSSOP	0.173 "	4.4 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.00
		10	$ 0.89
		25	$ 0.85
		100	$ 0.69
		250	$ 0.65
		500	$ 0.57
		1000	$ 0.45
		2500	$ 0.42
		5000	$ 0.40
Texas Instruments	TUBE	1	$ 0.90
		100	$ 0.61
		250	$ 0.47
		1000	$ 0.32

Description

General part information

SN74AHC74Q-Q1 Series

The SN74AHC74 dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The SN74AHC74 dual positive-edge-triggered device is a D-type flip-flop.

Documents

Technical documentation and resources

Design Summary for WCSP Little Logic (Rev. B)

Product overview

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

SNx4AHC74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset datasheet (Rev. N)

Data sheet

Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)

Application note

SN74AHC74N

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SN74AHC74N

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Technical Specifications

SN74AHC74Q-Q1 Series

Pricing

Description

SN74AHC74Q-Q1 Series

Documents

Design Summary for WCSP Little Logic (Rev. B)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Little Logic Guide 2018 (Rev. G)

How to Select Little Logic (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

Selecting the Right Level Translation Solution (Rev. A)

Implications of Slow or Floating CMOS Inputs (Rev. E)

LOGIC Pocket Data Book (Rev. B)

Logic Guide (Rev. AB)

AHC/AHCT Designer's Guide February 2000 (Rev. D)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Power-Up Behavior of Clocked Devices (Rev. B)

Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)

Texas Instruments Little Logic Application Report

Live Insertion

CMOS Power Consumption and CPD Calculation (Rev. B)

SNx4AHC74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset datasheet (Rev. N)

Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)

SN74AHC74Q-Q1 Series