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64-TQFP-PJW
Integrated Circuits (ICs)

TNETE2201BPJW

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Texas Instruments

1.25-GIGABIT ETHERNET TRANSCEIVER

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64-TQFP-PJW
Integrated Circuits (ICs)

TNETE2201BPJW

Active
Texas Instruments

1.25-GIGABIT ETHERNET TRANSCEIVER

Technical Specifications

Parameters and characteristics for this part

SpecificationTNETE2201BPJW
Data Rate1.25 Gbps
DuplexHalf
Mounting TypeSurface Mount
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case64-TQFP Exposed Pad
ProtocolGigabit Ethernet
Supplier Device Package64-HTQFP (10x10)
TypeTransceiver
Voltage - Supply [Max]3.47 V
Voltage - Supply [Min]3.14 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 160$ 8.07
Texas InstrumentsJEDEC TRAY (10+1) 1$ 8.26
100$ 6.74
250$ 5.29
1000$ 4.49

Description

General part information

TNETE2201B Series

The TNETE2201B gigabit Ethernet transceiver provides for ultra high-speed bidirectional point-to-point data transmission. This device is based on the timing requirements of the proposed 10-bit interface specification by the P802.3z Gigabit Task Force.

The intended application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled-impedance media of approximately 50. The transmission media can be printed-circuit board traces, back planes, cables, or fiber optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TNETE2201B performs the data serialization and deserialization (SERDES) functions for the gigabit ethernet physical layer interface. The transceiver operates at 1.25 Gbps (typical), providing up to 1000 Mbps of bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero (NRZ) at pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output with respect to two receive byte clocks (RBC0, RBC1), allowing a protocol device to clock the parallel bytes in RBC clock rising edges.