Specification	CDC2509CPWR

Differential - Input:Output	False
Divider/Multiplier	False
Frequency - Max [Max]	125 MHz
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	0 °C
Output	LVTTL
Package / Case	24-TSSOP
Package / Case	0.173 in, 4.4 mm
PLL	Yes with Bypass
Ratio - Input:Output	1:9
Supplier Device Package	24-TSSOP
Type	PLL Clock Driver
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

CDC2509C Series

1-to-9 PLL clock driver for SDRAM applications

Part	Type	Package / Case	Package / Case	Output	Ratio - Input:Output	Number of Circuits	Mounting Type	PLL	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Operating Temperature [Max]	Frequency - Max [Max]
Texas Instruments CDC2509APWR	PLL Clock Driver	24-TSSOP	0.173 in 4.4 mm	LVTTL	1:9	1	Surface Mount	Yes with Bypass	3.6 V	3 V	24-TSSOP	70 °C
Texas Instruments CDC2509BPW	PLL Clock Driver	24-TSSOP	0.173 in 4.4 mm	LVTTL	1:9	1	Surface Mount	Yes with Bypass	3.6 V	3 V	24-TSSOP	70 °C	125 MHz
Texas Instruments CDC2509CPWR	PLL Clock Driver	24-TSSOP	0.173 in 4.4 mm	LVTTL	1:9	1	Surface Mount	Yes with Bypass	3.6 V	3 V	24-TSSOP	85 °C	125 MHz

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	2000	$ 5.41
Texas Instruments	LARGE T&R	1	$ 8.72
		100	$ 7.11
		250	$ 5.59
		1000	$ 4.74

Description

General part information

CDC2509C Series

The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Documents

Technical documentation and resources

CDC2509C: 3.3-V Phase-Lock Loop Clock Driver datasheet (Rev. A)

Data sheet