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Technical Specifications
Parameters and characteristics for this part
| Specification | CDC111FNR |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 500 MHz |
| Input | LVPECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | LVPECL |
| Package / Case | 28-LCC (J-Lead) |
| Ratio - Input:Output | 1:9 |
| Supplier Device Package | 28-PLCC (11.51x11.51) |
| Type | Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
CDC111 Series
The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50-transmission lines.
When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).
The VREFoutput can be strapped to the CLKIN\ input for a single-ended CLKIN input.
Documents
Technical documentation and resources
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