Integrated Circuits (ICs)

SN74ABT657ADWR

Obsolete

Texas Instruments

BUS XCVR SINGLE 8-CH 3-ST 24-PIN SOIC T/R

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Integrated Circuits (ICs)

SN74ABT657ADWR

Obsolete

Texas Instruments

BUS XCVR SINGLE 8-CH 3-ST 24-PIN SOIC T/R

Deep-Dive with AI

DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74ABT657ADWR

Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	3-State
Package / Case	24-SOIC
Package / Case [custom]	7.5 mm
Package / Case [custom]	0.295 in
Supplier Device Package	24-SOIC
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ABT657A Series

Octal Transceivers With Parity Generators/Checkers And 3-State Outputs

Part	Number of Bits per Element	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Supplier Device Package	Package / Case [custom]	Package / Case	Package / Case [custom]	Mounting Type	Number of Elements	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case
Texas Instruments SN74ABT657ADW	8	64 mA	32 mA	3-State	24-SOIC	7.5 mm	24-SOIC	0.295 in	Surface Mount	1	4.5 V	5.5 V	85 °C	-40 °C
Texas Instruments SN74ABT657ANT	8	64 mA	32 mA	3-State	24-PDIP		24-DIP		Through Hole	1	4.5 V	5.5 V	85 °C	-40 °C	0.3 in	7.62 mm
Texas Instruments SN74ABT657ADBR	8	64 mA	32 mA	3-State	24-SSOP		24-SSOP		Surface Mount	1	4.5 V	5.5 V	85 °C	-40 °C
Texas Instruments SN74ABT657ADWR	8	64 mA	32 mA	3-State	24-SOIC	7.5 mm	24-SOIC	0.295 in	Surface Mount	1	4.5 V	5.5 V	85 °C	-40 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

SN74ABT657A Series

The 'ABT657A transceivers have eight noninverting buffers with parity-generator/checker circuits and control signals. The transmit/receive (T/R\) input determines the direction of data flow. When T/R\ is high, data flows from the A port to the B port (transmit mode); when T/R\ is low, data flows from the B port to the A port (receive mode). When the output-enable (OE\) input is high, both the A and B ports are in the high-impedance state.

Odd or even parity is selected by a logic high or low level on the ODD/EVEN\ input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.

In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN\. For example, if ODD/EVEN\ is low (even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.

Documents

Technical documentation and resources