Specification	SN74AS175BN

Clock Frequency	100 MHz
Current - Output High, Low [custom]	20 mA
Current - Output High, Low [custom]	2 mA
Current - Quiescent (Iq)	34 mA
Max Propagation Delay @ V, Max CL	10 ns
Mounting Type	Through Hole
Number of Bits per Element	4
Number of Elements	1
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output Type	Complementary
Package / Case	0.3 in
Package / Case	16-DIP
Package / Case	7.62 mm
Supplier Device Package	16-PDIP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74AS175B Series

Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear

Part	Number of Elements	Trigger Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Type	Clock Frequency	Number of Bits per Element	Max Propagation Delay @ V, Max CL	Current - Quiescent (Iq)	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case [x]	Package / Case [y]	Supplier Device Package	Output Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case	Package / Case
Texas Instruments SN74AS175N
Texas Instruments SN74AS175BD	1	Positive Edge	4.5 V	5.5 V	D-Type	100 MHz	4	10 ns	34 mA	Surface Mount	70 °C	0 °C	16-SOIC	0.154 in	3.9 mm	16-SOIC	Complementary	20 mA	2 mA
Texas Instruments SN74AS175BN	1	Positive Edge	4.5 V	5.5 V	D-Type	100 MHz	4	10 ns	34 mA	Through Hole	70 °C	0 °C	16-DIP			16-PDIP	Complementary	20 mA	2 mA	0.3 in	7.62 mm
Texas Instruments SN74AS175BNSR	1	Positive Edge	4.5 V	5.5 V	D-Type	100 MHz	4	10 ns	34 mA	Surface Mount	70 °C	0 °C	16-SOIC			16-SO	Complementary	20 mA	2 mA	0.209 "	5.3 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	225	$ 4.59
Texas Instruments	TUBE	1	$ 4.93
		100	$ 4.02
		250	$ 3.16
		1000	$ 2.68

Description

General part information

SN74AS175B Series

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

Documents

Technical documentation and resources

Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. E)

Data sheet