
CDCP1803RGET
Active1:3 LVPECL CLOCK BUFFER WITH PROGRAMABLE DIVIDER
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CDCP1803RGET
Active1:3 LVPECL CLOCK BUFFER WITH PROGRAMABLE DIVIDER
Technical Specifications
Parameters and characteristics for this part
| Specification | CDCP1803RGET |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 800 MHz |
| Input | LVDS, CML, SSTL-2, LVCMOS, VML, HSTL, LVTTL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVPECL |
| Package / Case | 24-VFQFN Exposed Pad |
| Ratio - Input:Output [custom] | 1:3 |
| Supplier Device Package | 24-VQFN (4x4) |
| Type | Fanout Buffer (Distribution), Divider, Multiplexer |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 8.40 | |
| 10 | $ 7.58 | |||
| 25 | $ 7.23 | |||
| 100 | $ 6.28 | |||
| Digi-Reel® | 1 | $ 8.40 | ||
| 10 | $ 7.58 | |||
| 25 | $ 7.23 | |||
| 100 | $ 6.28 | |||
| Tape & Reel (TR) | 250 | $ 6.00 | ||
| 500 | $ 5.47 | |||
| 1250 | $ 4.76 | |||
| Texas Instruments | SMALL T&R | 1 | $ 6.43 | |
| 100 | $ 5.24 | |||
| 250 | $ 4.12 | |||
| 1000 | $ 3.49 | |||
Description
General part information
CDCP1803 Series
The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] andY[2:0]with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines.
The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.
The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] andY[2:0]with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines.
Documents
Technical documentation and resources