SN74AHC16373DGGR
Active16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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SN74AHC16373DGGR
Active16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHC16373DGGR |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low [custom] | 8 mA |
| Current - Output High, Low [custom] | 8 mA |
| Delay Time - Propagation | 1 ns |
| Independent Circuits | 2 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 48-TFSOP |
| Package / Case | 0.24 in |
| Package / Case [custom] | 6.1 mm |
| Supplier Device Package | 48-TSSOP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.62 | |
| 10 | $ 1.45 | |||
| 25 | $ 1.38 | |||
| 100 | $ 1.13 | |||
| 250 | $ 1.06 | |||
| 500 | $ 0.93 | |||
| 1000 | $ 0.74 | |||
| Digi-Reel® | 1 | $ 1.62 | ||
| 10 | $ 1.45 | |||
| 25 | $ 1.38 | |||
| 100 | $ 1.13 | |||
| 250 | $ 1.06 | |||
| 500 | $ 0.93 | |||
| 1000 | $ 0.74 | |||
| Tape & Reel (TR) | 2000 | $ 0.61 | ||
| Texas Instruments | LARGE T&R | 1 | $ 1.13 | |
| 100 | $ 0.93 | |||
| 250 | $ 0.67 | |||
| 1000 | $ 0.50 | |||
Description
General part information
SN74AHC16373 Series
The 'AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
Documents
Technical documentation and resources
