Integrated Circuits (ICs)

SN74ALVCH16820DGGR

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3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS

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Search across all available documentation for this part.

DocumentsInput and Output Characteristics of Digital Integrated Circuits Semiconductor Packing Material Electrostatic Discharge (ESD) Protection +18

Integrated Circuits (ICs)

SN74ALVCH16820DGGR

Active

Texas Instruments

3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsInput and Output Characteristics of Digital Integrated Circuits Semiconductor Packing Material Electrostatic Discharge (ESD) Protection +18

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74ALVCH16820DGGR

Clock Frequency	150 MHz
Current - Output High, Low	24 mA
Function	Standard
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	4.8 ns
Mounting Type	Surface Mount
Number of Bits per Element	10
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Non-Inverted
Package / Case	6.1 mm
Package / Case	0.24 in
Package / Case	56-TFSOP
Supplier Device Package	56-TSSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74ALVCH16820 Series

3.3-V 10-Bit Flip-Flop with Dual Outputs and 3-State Outputs

Part	Supplier Device Package	Function	Output Type	Number of Bits per Element	Clock Frequency	Number of Elements	Max Propagation Delay @ V, Max CL	Package / Case	Package / Case	Package / Case	Current - Output High, Low	Mounting Type	Input Capacitance	Trigger Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Type	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SN74ALVCH16820DL	56-SSOP	Standard	Non-Inverted Tri-State	10	150 MHz	1	4.8 ns	0.295 in	56-BSSOP	7.5 mm	24 mA	Surface Mount	3.5 pF	Positive Edge	1.65 V	3.6 V	D-Type	85 °C	-40 °C
Texas Instruments SN74ALVCH16820DLR	56-SSOP	Standard	Non-Inverted Tri-State	10	150 MHz	1	4.8 ns	0.295 in	56-BSSOP	7.5 mm	24 mA	Surface Mount	3.5 pF	Positive Edge	1.65 V	3.6 V	D-Type	85 °C	-40 °C
Texas Instruments SN74ALVCH16820DGGR	56-TSSOP	Standard	Non-Inverted Tri-State	10	150 MHz	1	4.8 ns	0.24 in	56-TFSOP	6.1 mm	24 mA	Surface Mount	3.5 pF	Positive Edge	1.65 V	3.6 V	D-Type	85 °C	-40 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 4.51
	Digi-Reel®	1	$ 4.51
	Tape & Reel (TR)	2000	$ 2.26
Texas Instruments	LARGE T&R	1	$ 3.40
		100	$ 2.98
		250	$ 2.09
		1000	$ 1.69

Description

General part information

SN74ALVCH16820 Series

This 10-bit flip-flop is designed for 1.65-V to 3.6-V VCCoperation.

The flip-flops of the SN74ALVCH16820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

Documents

Technical documentation and resources

SN74ALVCH16820DGGR

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SN74ALVCH16820DGGR

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Technical Specifications

SN74ALVCH16820 Series

Pricing

Description

SN74ALVCH16820 Series

Documents

Input and Output Characteristics of Digital Integrated Circuits

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Understanding Advanced Bus-Interface Products Design Guide

SN74ALVCH16820 datasheet (Rev. G)

Live Insertion

Logic Guide (Rev. AB)

Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)

ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

CMOS Power Consumption and CPD Calculation (Rev. B)

TI SN74ALVC16835 Component Specification Analysis for PC100

Power-Up Behavior of Clocked Devices (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Standard Linear & Logic for PCs, Servers & Motherboards

Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)

LOGIC Pocket Data Book (Rev. B)

SN74ALVCH16820 Series