Specification	SN74ALVCH16260DL

Circuit	12:24
Current - Output High, Low	24 mA
Delay Time - Propagation	1 ns
Independent Circuits	1
Logic Type	D-Type, Addressable
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	0.295 in
Package / Case	56-BSSOP
Package / Case	7.5 mm
Supplier Device Package	56-SSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74ALVCH16260 Series

12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs

Part	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low	Circuit	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Independent Circuits	Delay Time - Propagation	Package / Case	Package / Case	Package / Case	Mounting Type	Logic Type
Texas Instruments SN74ALVCH16260DL	Tri-State	85 °C	-40 °C	24 mA	12:24	1.65 V	3.6 V	56-SSOP	1	1 ns	0.295 in	56-BSSOP	7.5 mm	Surface Mount	D-Type Addressable
Texas Instruments SN74ALVCH16260DGR
Texas Instruments SN74ALVCH16260DLR	Tri-State	85 °C	-40 °C	24 mA	12:24	1.65 V	3.6 V	56-SSOP	1	1 ns	0.295 in	56-BSSOP	7.5 mm	Surface Mount	D-Type Addressable
Texas Instruments SN74ALVCH16260DGG

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 2.40
		20	$ 2.16
		40	$ 2.04
		100	$ 1.73
		260	$ 1.63
		500	$ 1.42
		1000	$ 1.18
		2500	$ 1.10
		5000	$ 1.06
Texas Instruments	TUBE	1	$ 1.80
		100	$ 1.49
		250	$ 1.07
		1000	$ 0.81

Description

General part information

SN74ALVCH16260 Series

This 12-bit to 24-bit multiplexed D-type latch is designed for 1.65-V to 3.6-V VCCoperation.

The SN74ALVCH16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications.

Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.

Documents

Technical documentation and resources

SN74ALVCH16260DL

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SN74ALVCH16260DL

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Technical Specifications

SN74ALVCH16260 Series

Pricing

Description

SN74ALVCH16260 Series

Documents

Datasheet

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

Live Insertion

Power-Up Behavior of Clocked Devices (Rev. B)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Logic Guide (Rev. AB)

Standard Linear & Logic for PCs, Servers & Motherboards

TI SN74ALVC16835 Component Specification Analysis for PC100

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Understanding Advanced Bus-Interface Products Design Guide

LOGIC Pocket Data Book (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

CMOS Power Consumption and CPD Calculation (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)

SN74ALVCH16260 Series