
RM41L232BPZT
Active16/32 BIT RISC FLASH MCU, ARM CORTEX-R4F
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RM41L232BPZT
Active16/32 BIT RISC FLASH MCU, ARM CORTEX-R4F
Technical Specifications
Parameters and characteristics for this part
| Specification | RM41L232BPZT |
|---|---|
| Connectivity | LINbus, SCI, SPI, CANbus, MibSPI, UART/USART |
| Core Processor | ARM® Cortex®-R4 |
| Core Size [Max] | 32 Bit |
| Core Size [Min] | 16 Bit |
| Data Converters [custom] | 16 |
| Data Converters [custom] | 12 b |
| EEPROM Size | 16 K |
| Mounting Type | Surface Mount |
| Number of I/O | 45 |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | External |
| Package / Case | 100-LQFP |
| Peripherals | WDT, POR |
| Program Memory Size | 128 KB |
| Program Memory Type | FLASH |
| Speed | 80 MHz |
| Supplier Device Package | 100-LQFP (14x14) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.14 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 7.05 | |
| 10 | $ 6.37 | |||
| 25 | $ 6.07 | |||
| 90 | $ 5.27 | |||
| 270 | $ 5.21 | |||
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 7.67 | |
| 100 | $ 6.26 | |||
| 250 | $ 4.92 | |||
| 1000 | $ 4.17 | |||
Description
General part information
RM41L232 Series
The RM41L232 device is a high-performance microcontroller for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and Memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
The RM41L232 device integrates the ARM Cortex-R4 CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 80 MHz, providing up to 132 DMIPS. The device operates in little-endian (LE) mode.
The RM41L232 device has 128KB of integrated flash and 32KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (the same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of 80 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes throughout the supported frequency range.
Documents
Technical documentation and resources