Integrated Circuits (ICs)

CD74HCT564E

Active

HIGH SPEED CMOS LOGIC OCTAL POSITIVE-EDGE-TRIGGERED D-TYPE INVERTING FLIP-FLOPS WITH 3-STATE OUTPUTS

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Search across all available documentation for this part.

DocumentsUnderstanding and Interpreting Standard-Logic Data Sheets (Rev. C)Implications of Slow or Floating CMOS Inputs (Rev. E)+11

Integrated Circuits (ICs)

CD74HCT564E

Active

Texas Instruments

HIGH SPEED CMOS LOGIC OCTAL POSITIVE-EDGE-TRIGGERED D-TYPE INVERTING FLIP-FLOPS WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsUnderstanding and Interpreting Standard-Logic Data Sheets (Rev. C)Implications of Slow or Floating CMOS Inputs (Rev. E)+11

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CD74HCT564E

Clock Frequency	50 MHz
Current - Output High, Low [custom]	6 mA
Current - Output High, Low [custom]	6 mA
Current - Quiescent (Iq)	8 ÁA
Function	Standard
Input Capacitance	10 pF
Max Propagation Delay @ V, Max CL	35 ns
Mounting Type	Through Hole
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Tri-State, Inverted
Package / Case	20-DIP
Package / Case	7.62 mm
Package / Case	0.3 in
Supplier Device Package	20-PDIP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

CD74HCT564 Series

High Speed CMOS Logic Octal Positive-Edge-Triggered D-Type Inverting Flip-Flops with 3-State Outputs

Part	Number of Elements	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Quiescent (Iq)	Trigger Type	Supplier Device Package	Function	Operating Temperature [Max]	Operating Temperature [Min]	Max Propagation Delay @ V, Max CL	Package / Case	Package / Case [y]	Package / Case [y]	Number of Bits per Element	Output Type	Input Capacitance	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Type	Clock Frequency	Package / Case	Package / Case
Texas Instruments CD74HCT564M	1	6 mA	6 mA	8 ÁA	Positive Edge	20-SOIC	Standard	125 °C	-55 °C	14 ns	20-SOIC	0.295 in	7.5 mm	8	Tri-State Inverted	10 pF	Surface Mount	4.5 V	5.5 V	D-Type	50 MHz
Texas Instruments CD74HCT564MG4	1	6 mA	6 mA	8 ÁA	Positive Edge	20-SOIC	Standard	125 °C	-55 °C	35 ns	20-SOIC	0.295 in	7.5 mm	8	Tri-State Inverted	10 pF	Surface Mount	4.5 V	5.5 V	D-Type	50 MHz
Texas Instruments CD74HCT564E	1	6 mA	6 mA	8 ÁA	Positive Edge	20-PDIP	Standard	125 °C	-55 °C	35 ns	20-DIP			8	Tri-State Inverted	10 pF	Through Hole	4.5 V	5.5 V	D-Type	50 MHz	7.62 mm	0.3 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 2.22
		20	$ 1.99
		40	$ 1.88
		100	$ 1.60
		260	$ 1.50
		281	$ 1.07
		500	$ 1.32
		1000	$ 1.09
		2500	$ 1.01
		5000	$ 0.98
Texas Instruments	TUBE	1	$ 1.83
		100	$ 1.51
		250	$ 1.09
		1000	$ 0.82

Description

General part information

CD74HCT564 Series

High Speed CMOS Logic Octal Positive-Edge-Triggered D-Type Inverting Flip-Flops with 3-State Outputs

Documents

Technical documentation and resources

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

CDx4HC534, CDx4HCT534, CDx4HC564, CDx4HCT564 High-Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered datasheet (Rev. E)

Data sheet

CD74HCT564E

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CD74HCT564E

Deep-Dive with AI

Technical Specifications

CD74HCT564 Series

Pricing

Description

CD74HCT564 Series

Documents

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Implications of Slow or Floating CMOS Inputs (Rev. E)

CDx4HC534, CDx4HCT534, CDx4HC564, CDx4HCT564 High-Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered datasheet (Rev. E)

CMOS Power Consumption and CPD Calculation (Rev. B)

Signal Switch Data Book (Rev. A)

Power-Up Behavior of Clocked Devices (Rev. B)

Designing With Logic (Rev. C)

SN54/74HCT CMOS Logic Family Applications and Restrictions

TI IBIS File Creation, Validation, and Distribution Processes

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

LOGIC Pocket Data Book (Rev. B)

Logic Guide (Rev. AB)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

CD74HCT564 Series