SN65LVDT352PWR
ActiveQUAD RECEIVER WITH -4 TO 5-V COMMON-MODE RANGE
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SN65LVDT352PWR
ActiveQUAD RECEIVER WITH -4 TO 5-V COMMON-MODE RANGE
Technical Specifications
Parameters and characteristics for this part
| Specification | SN65LVDT352PWR |
|---|---|
| Data Rate | 560 Mbps |
| Mounting Type | Surface Mount |
| Number of Drivers/Receivers [custom] | 0 |
| Number of Drivers/Receivers [custom] | 4 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 24-TSSOP |
| Package / Case | 0.173 in, 4.4 mm |
| Protocol | LVDS |
| Receiver Hysteresis | 50 mV |
| Supplier Device Package | 24-TSSOP |
| Type | Receiver |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2000 | $ 2.36 | |
| Texas Instruments | LARGE T&R | 1 | $ 3.56 | |
| 100 | $ 3.12 | |||
| 250 | $ 2.18 | |||
| 1000 | $ 1.76 | |||
Description
General part information
SN65LVDT352 Series
The SN65LVDS348, SN65LVDT348, SN65LVDS352, and SN65LVDT352 are high-speed, quadruple differential receivers with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The ’348 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The ’352 adds two additional VCCand GND pins in a 24-pin package to provide higher data transfer rates with multiple receivers in operation. All offer a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110-line termination resistor.
These receivers also provide 3x the standard’s minimum common-mode noise voltage tolerance. The –4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface.
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range.
Documents
Technical documentation and resources