
CD74HC75M96
ActiveHIGH SPEED CMOS LOGIC DUAL 2-BIT BISTABLE TRANSPARENT LATCHES
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CD74HC75M96
ActiveHIGH SPEED CMOS LOGIC DUAL 2-BIT BISTABLE TRANSPARENT LATCHES
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC75M96 |
|---|---|
| Circuit | 2:2 |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Output High, Low [custom] | 5.2 mA |
| Delay Time - Propagation | 10 ns |
| Independent Circuits | 2 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Differential |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 16-SOIC |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.86 | |
| 10 | $ 0.76 | |||
| 25 | $ 0.71 | |||
| 100 | $ 0.58 | |||
| 250 | $ 0.54 | |||
| 500 | $ 0.46 | |||
| 1000 | $ 0.37 | |||
| Digi-Reel® | 1 | $ 0.86 | ||
| 10 | $ 0.76 | |||
| 25 | $ 0.71 | |||
| 100 | $ 0.58 | |||
| 250 | $ 0.54 | |||
| 500 | $ 0.46 | |||
| 1000 | $ 0.37 | |||
| Tape & Reel (TR) | 2500 | $ 0.20 | ||
| 5000 | $ 0.19 | |||
| 12500 | $ 0.18 | |||
| 25000 | $ 0.17 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.32 | |
| 100 | $ 0.25 | |||
| 250 | $ 0.18 | |||
| 1000 | $ 0.13 | |||
Description
General part information
CD74HC75 Series
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\ and 2E\) is LOW the output is not affected.
Documents
Technical documentation and resources